1. Technical Field
The exemplary embodiments of the present invention relate to semiconductor integration circuit apparatus, and more particularly, to a combined memory block including a variable resistance cell and a data processing system including the same.
2. Related Art
Memory devices are classified into random access memories (RAMs), which are volatile memories having data erased upon power off and read only memories (ROMs), which are nonvolatile memories that retain data upon power off. Here, dynamic RAM (DRAM) devices are representative RAMs and flash memory devices are representative ROMs.
While DRAM devices are advantageous due to their high speed operation from having easier random data access, DRAMs use a periodic refresh due to their volatile property and use large capacity capacitors.
On the other hand, while flash memory devices are advantageous for high integration density and avoidance of refresh operations, flash memory devices use a high operation voltage due to having a stack structure of two gates compared to a power voltage and use a separate boosting circuit for generating a voltage used for a read and write operation. In addition, since it is difficult to randomly access flesh memory devices, a program is performed for a page unit at a time and thus, an operation speed thereof is relatively slow.
As sizes of semiconductor memory devices gradually decrease, the implementation of a system on chip (SOC) in which function blocks having various functions are integrated on one chip is becoming more popular.
More specifically, a SOC type data processing system has a structure in which basic memories and various types of memories and non-memory chips of different functions are combined.
However, since chips having different driving conditions are mounted in a data processing system, separate driving circuits are used and thus the manufacturing process of the data processing system may become complicated and costly.